The present invention relates to a method of driving an electrically alterable read only memory (hereinafter referred to as EAROM) formed of metal-silicon nitride-silicon oxide-semiconductor (hereinafter referred to as MNOS) transistors or the like at the time of partially erasing (word erasing).
FIG. 1 shows a cross-section of a MNOS transistor structure used for an EAROM cell of this kind. Referring to FIG. 1, there are shown a gate electrode 1A, a silicon nitride Si.sub.3 N.sub.4 layer 1B, a silicon oxide SiO.sub.2 layer 1C, a source 1D, a drain 1E, a substrate 1F and a wafer substrate 1G.
When a voltage V.sub.p is applied to the gate 1A of the MNOS transistor and a potential of zero volts is applied to the substrate 1F, source 1D and drain 1F, electric charges are trapped at the interface of the silicon oxide SiO.sub.2 layer 1C and the silicon nitride Si.sub.3 N.sub.4 layer 1B. When, for example, the potential V.sub.p of +25 volts is applied to the gate of an N-channel MNOS transistor, electrons are trapped at the boundary between the SiO.sub.2 layer 1C and the Si.sub.3 N.sub.4 layer 1B. This condition is hereinafter called a "written state" of memory and defined as a stored condition of logic "1." This voltage V.sub.p varies depending on the kind of the element used, the duration of the potential application, etc.
On the other hand, when the voltage V.sub.p is applied to the substrate 1F with the gate 1A at zero volts and the source 1D and the drain 1E are brought into an open condition, the trapped charges disappear from the boundary between the silicon oxide SiO.sub.2 layer 1C and the silicon nitride Si.sub.3 N.sub.4 layer 1B. Such a condition is hereinafter referred to as an "erased state" of memory and defined as a stored condition of logic "0."
If a certain voltage V.sub.wd is applied to the source 1D and drain 1E under the condition that there is no potential difference between the gate 1A and substrate 1F of the MNOS transistor or even that the voltage V.sub.p is applied to the gate 1A with the substrate 1F at zero volts, the stored condition of the memory is not changed from logic "0" to logic "1" or vice versa. This corresponds to the case where, for example, an N-channel MNOS transistor is applied with 25 volts of V.sub.p and 20 volts of V.sub.wd. The voltage V.sub.wd varies depending on the kind of the element, etc.
If the voltage V.sub.p is applied to the substrate 1F with the gate at zero volts under the condition that the voltage V.sub.wd is applied to the source 1D and drain 1E, the content of the memory is erased as apparent from the structure.
In the case where an integrated memory array is made of such memory cells and only selected memory cells are desired to be erased for rewriting, the application of voltage must be carried out in a mode (non-erasing mode) at which the contents of the other non-selected memory cells are not erased.
FIG. 2 is a timing chart of signals according to a conventional memory driving method, which shows the relation between the signals to be applied to non-selected memory cells (not to be erased) when some selected memory cells are in the erase state. In the figure, V1 is an erasing operation signal to be applied to the memory. When the signal V1 is a "1" level, an erasing operation is performed so that the contents of selected memory cells of the memory are erased. VA is a voltage to be applied to the gates 1A of non-selected memory cells and VB is a voltage to be applied to the substrates 1F of those non-selected memory cells. When the erasing operation signal V1 becomes logic "1," the voltages VA and VB at the gates 1A and substrates 1F of the non-selected memory cells rise to the same voltage V.sub.p (at time instant T.sub.1). When the erasing operation signal V1 becomes logic "0," the voltages VA and VB fall off to zero volts (at time instant T.sub.2). At this time, the sources 1D and drains 1E of the non-selected memory cells are in the open condition.
Since the voltages at the gate 1A and substrate 1F change quite similarly in the non-erasing mode as shown in FIG. 2, there is no potential difference between the gate 1A and the substrate 1F and thus there is no effect on the stored condition of the non-selected memory cells.
In practice, however, even when the voltage V.sub.p is simultaneously applied to the gate 1A and the substrate 1F, a well capacity or the like between the substrate 1F and the wafer substrate 1G frequently causes a small time difference t.sub.d between the gate voltage VA and the substrate voltage VB, as shown in FIG. 3. In a transient condition during the time t.sub.d, since the voltage V.sub.p is applied to the gate 1A and the substrate 1F is at zero volts, the corresponding memory cell is instantly brought into the write condition if the source 1D and the drain 1E are at zero volts. Through this time difference t.sub.d is generally much shorter than the time T.sub.w that it takes to write, the stored condition of some non-selected memory cells whose gates 1A are applied with this voltage V.sub.p may be changed if such a transient write operation occurs several times in sequence. This fact has affected so far the normal operation of the EAROM to reduce its storage time.
If, for example, the leading edge of the voltage V.sub.p at the gates 1A of some memory cells is 100 .mu.sec faster than that at the substrates 1F, that is, there is the time difference t.sub.d of 100 .mu.sec, and if the T.sub.w of memory is 250 msec, then the ratio T.sub.w /t.sub.d is 2500, which means that when erasing operation on the other memory cells is performed 2500 times or more, the condition of the non-selected memory cells not to be erased changes to logic "1" from logic "0."
In addition, there is a possibility that the substrate voltage VB instantly changes to the V.sub.p with zero gate voltage. In this case, the corresponding memory cell is brought into the erased condition in a moment.